DWMC-16 v2 Design Part 5: Operations and OpCodes
This section contains a basic design of the DWMC-16 Operations and their OpCode design, meaning how operations are going to be represented in memory.
design¶
DWMC-16 v2 Design Part 4b: Corrections
While I am thinking about the Memory Addressing Modes, I noticed that that if I am to use Relative Addressing, that is an address relative to the Program Counter, I may need to add a PC Offset Register in the Special Use Register Block. So I had to modify the basic design a little to add this new register.
DWMC-16 v2 Design Part 4: IO System
This is the general design for the IO systems used by the DWMC-16.
As the IO System is mapped into a sector in memory, it does share the same subdivision into 4 kiWord memory blocks, with each block of memory used to address one IO module.
DWMC-16 v2 Design Part 3: Memory
This section is about the design of the Memory System of the DWMC-16. It will discuss the Memory, the DMA Controller and the Memory Management Unit.
DWMC-16 v2 Design Part 2c: Corrections
Well... It seems that I have forgotten to add a few things to the ALU that should be part of it... oops...