The execution of all operations are split into phases called instruction cycles. The various types of instructions have a varying number of instruction cycles.
Each instruction cycle takes at least two clock cycles to complete.
So, I have done some thinking, concerning my decision to add four Index/Offset Registers/Secondary Stack Pointers. And since I want to be able to write a nice, simple version of Forth for the DWMC-16... I decided that I would throw the Special Registers out of memory and put them into the second Register Bank, where I can do a bit more with them, without the need to load and reload them. Largely this is to cut down on commands to load addresses into the Index Registers...
With the last Post, I decided that I would modify the system a little, with a modification to add nor three bit four Secondary Stack Pointers, simply by removing the PC Offset Register from the Special Registers. This does not however mean that I remove the relative jumps, those are dealt with separately.
This post is the result of me listening to this week's episode of the Advent of a computing podcast, the Jupiter Ace. The Ace was a small micro from 1982/83, designed by two guys that worked on the software and hardware of the Sinclair ZX-81. The hardware was pretty much the same as the ZX-81, but it had one big difference.
Instead of BASIC, the Ace ran Forth, a stack based language that is small, easy and fast.
This section contains a basic design of the DWMC-16 Operations and their OpCode design, meaning how operations are going to be represented in memory.